1. Field of the Invention
The present invention relates to an image pickup apparatus for picking up an object image.
2. Related Background Art
Conventionally, a charge coupled device (CCD) has been used as a solid-state image pickup device frequently because the CCD has a high signal to noise (S/N) ratio. On the other hand, the so-called amplification-type solid-state image pickup apparatus has been also developed because of its simple usage and of its low power consumption. The amplification-type solid-state image pickup apparatus is the device that introduces signal charges accumulated on light-receiving pixels to the control electrodes of transistors provided at pixel portions to output signals amplified by the transistors from their main electrodes. There are the following amplification-type solid-state image pickup apparatus: a static induction transistor (SIT) type image sensor using SITs as amplifying transistors (A. Yusa, J. Nishizawa et al., “SIT image sensor: Design consideration and characteristics,” IEEE trans. Vol. ED-33 pp. 735-742, Jun. 1986), a bipolar amplifying solid-state image sensor (BASIS) using bipolar transistors (N. Tanaka et al., “A 310 K pixel bipolar imager (BASIS),” IEEE Trans. Electron Devices, vol. 35, pp. 646-652, May 1990), a charge modulation device (CMD) using a junction-type field effect transistor (JFETs) in which control electrodes form depletion layers (Nakamura et al., “Gate Accumulation Type MOS Phototransistor Image Sensor”, National Conference of Television Society, 3-7, 1986), a complementary metal oxide semiconductor (CMOS) sensor using metal oxide semiconductor (MOS) transistors (S. K. Mendis, S. E. Kemeny and E. R. Fossum, “A 128×128 CMOS active image sensor for highly integrated imaging systems,” in IEDM Tech. Dig., 1993, pp. 583-586), and the like. In particular, the CMOS sensor matches CMOS processes well and peripheral CMOS circuits can be formed on the chip of the CMOS sensor. Accordingly, the CMOS sensors are being energetically developed. A common problem of the amplification-type solid-state image pickup apparatus is that the amplifying transistors provide their respective output offsets to produce a fixed pattern noise (FPN) in signals of the image sensor. Conventionally, various signal reading circuits have been devised to remove the FPN. Besides, the CMOS sensor has the disadvantage that the number of transistors for constituting a pixel is large to make it difficult to reduce the area of the pixel.
FIG. 8 is a circuit diagram showing a conventional CMOS image sensor. In FIG. 8, a reference numeral 1 designates unit pixels. In FIG. 8, it is supposed to simplify descriptions that the CMOS image sensor has 2×2 unit pixels. A reference numeral 2 designates photodiodes for receiving light to accumulate signal charges. A reference numeral 3 designates MOS transistors for amplifying the signal charges. A reference numeral 4 designates transferring MOS transistors for transferring the signal charges accumulated in the photodiodes 2 to the gate electrode portions of the amplifying MOS transistors 3. A reference numeral 5 designates resetting MOS transistors for resetting the gate electrode potential of the amplifying MOS transistors 3. A reference numeral 6 designates electric power potential supplying lines. The drain electrodes of the amplifying MOS transistors 3 are connected to the electric power potential supplying lines 6. A reference numeral 7 designates pixel output lines. A reference numeral 8 designates switching MOS transistors for supplying reset electric potential through the output lines 7. A reference numeral 9 designates constant current supplying MOS transistors for supplying constant currents to the pixel output lines 7. A constant current supplying MOS transistor 9 makes the amplifying MOS transistors 3 of selected pixels operate as source followers through a switching MOS transistor 8, and causes the electric potential having a certain voltage difference from the gate potential of the amplifying MOS transistors 3 to appear on an output line 7. A reference numeral 10 designates transfer control lines for controlling the gate potential of the transferring MOS transistors 4. A reference numeral 11 designates reset control lines for controlling the gate potential of the resetting MOS transistors 5. A reference numeral 12 designates a control line for supplying pulses for controlling the gate electrodes of the switching MOS transistors 8. A reference numeral 13 designates a constant voltage supplying line for supplying a constant voltage to the gates of the MOS transistors 9 for making the MOS transistors 9 operate in their saturation region in order that the MOS transistors 9 operate as constant current supplying sources. A reference numeral 14 designates a pulse terminal for supplying transfer pulses to the transfer control lines 10. A reference numeral 15 designates a pulse supplying terminal for selecting all rows to be given a reset pulse. A reference numeral 16 designates a pulse supplying terminal for supplying a reset pulse to the reset control lines 11. A reference numeral 17 designates a vertical scanning circuit for selecting and scanning the rows of the pixels arranged in a matrix. A reference numeral 18 designates output lines of the vertical scanning circuit 17. A reference numeral 18-1 designates a first row selecting output line. A reference numeral 18-2 designates a second row selecting output line. A reference numeral 19 designates switching MOS transistors for introducing a pulse from the pulse terminal 14 to the control lines 10. A reference numeral 20 designates OR gates for receiving the outputs from the pulse supplying terminal 15 and from the vertical scanning circuit 17 as inputs thereto to designate a reset row. A reference numeral 21 designates switching MOS transistors for introducing a pulse from the pulse terminal 16 to the control lines 11. The gates of the MOS transistors 19 and 21 are connected to the row selecting output lines 18, and the row of the pixels to be driven is determined by the states of the row selecting output lines 18 and by the state of the terminal 15. Next, a reference numeral 22 designates readout circuits for reading out outputs from the pixels. A reference numeral 23 designates capacitors for holding reset signal outputs from the pixels. A reference numeral 24 designates capacitors for holding optical signal outputs from the pixels. A reference numeral 25 designates switching MOS transistors for turning on or off the electrical connections between the pixel output lines 7 and the capacitors 23. A reference numeral 26 designates switching MOS transistors for turning on or off the electrical connections between the pixel output lines 7 and the capacitors 24. A reference numeral 27 designates a noise output line to which reset outputs held by the capacitors 23 are led. A reference numeral 28 designates a signal output line to which optical signal outputs held by the capacitors 24 are led. A reference numeral 29 designates switching MOS transistors for turning on or off the electrical connections between the capacitors 23 and the noise output line 27. A reference numeral 30 designates switching MOS transistors for turning on or off the electrical connections between the capacitors 24 and the signal output line 28. A reference numeral 31 designates a noise output line resetting MOS transistor for resetting the electric potential of the noise output line 27. A reference numeral 32 designates a signal output line resetting MOS transistor for resetting the electric potential of the signal output line 28. A reference numeral 33 designates a power source terminal for supplying reset potential to the source electrodes of the resetting MOS transistors 31 and 32. A reference numeral 34 designates a horizontal scanning circuit for selecting sequentially the capacitors 23 and 24, which are provided at every column of the pixels arranged in the matrix, in order. A reference numeral 35-1 designates an output line for selecting a first column. A reference numeral 35-2 designates an output line for selecting a second column. The output lines 35-1 and 35-2 of the horizontal scanning circuit 34 are respectively connected to the gate of the switching MOS transistors 29 and 30. Moreover, a reference numeral 36 designates a pulse supplying terminal for applying pulses to the gates of the resetting MOS transistors 31 and 32. Reference numerals 37 and 38 designate pulse supplying terminals for applying pulses to the gates of the switching MOS transistors 25 and 26. A reference numeral 39 designates a differential amplifier for amplifying difference voltages between the noise output line 27 and the signal output line 28 and outputting the amplified difference voltages. A reference numeral 40 designates an output terminal of the differential amplifier 39. A reference numeral 41 designates a pulse supplying terminal to the gates of the MOS transistors 9. A reference numeral 42 designates a pulse supplying terminal to the gates of the MOS transistors 8. A reference numeral 43 designates a potential supplying terminal for supplying the reset potential to the pixel output lines 7 through the MOS transistors 8. Moreover, a reference numeral 44 designates the so-called floating diffusion (hereinafter, referred to as “FD”) where the drains of the MOS transistors 4 and 5 and the gates of the MOS transistors 3 are connected and where signal charges are transferred from the MOS transistors 4.
Next, the timing chart of FIG. 9 is referred while the operation of the sensor of FIG. 8 is described. Incidentally, it is supposed that all of the MOS transistors shown in FIG. 8 are N type ones, and that they are turned on when their gate potential is the High level and turned off when their gate potential is the Low level. The numbers indicating timing pulses in FIG. 9 are set to coincide with the numbers of the pulse input terminals in FIG. 8.
First, when the level of the first row selecting output line 18-1 turns to the High level by the operation of the vertical scanning circuit 17, the first row of the pixel matrix is selected. Moreover, at this time, the level of the terminal 41 is the Low level, and the level of the terminal 42 is the High level. Consequently, the electric potential of the pixel output lines 7 is determined in accordance with the potential supplied from the terminal 43 (t1). First, when the level of the terminal 15 turns to the High level, the High level is transferred to the MOS switches 21 of all of the rows through the OR gates 20 to turn on the MOS switches 21. The electric potential of the FD 44 of all of the pixels is reset to the electric potential of the terminal 43 by a pulse supplied from the terminal 16 (t2). Next, when the level of the terminal 15 turns to the Low level, only the MOS switch 21 at the first row, which is the selected row, would be in the ON state thereof. In this state, when the electric potential of the terminal 43 is raised by a certain voltage, and when a pulse is supplied from the terminal 16, the electric potential of the FD 44 of the pixels at the first row is reset to the electric potential of the terminal 43 (t3). Next, the level of the terminal 42 is turned to the Low level to turn off the MOS switches 8, and the electric potential of the terminal 41 is set to the electric potential which makes it possible that the MOS transistors 9 supply constant currents. At this time, the gate potential of the MOS transistors 3 at the first row has been reset to the potential higher than the gate potential of the MOS transistors 3 on the other rows. The MOS transistors 3 on the first row operate as the source followers, and the MOS transistors 3 on the other rows are in their OFF state. Consequently, the sources of the amplifying MOS transistors 3 at the pixels on the selected first row are connected to the constant current sources 9. Thereby, the source follower outputs of the pixels are output on the output lines 7 (t4). In this state, when a High pulse is applied to the terminal 37, the reset outputs of the first row pixels are stored in the capacitors 23 through the MOS transistors 25 (t5). Next, a High pulse is applied to the terminal 14. Thereby, the High pulse is transmitted to the control line 10 through the switching MOS transistor 19 of the first row. Then, the signal charges accumulated in the photodiodes 2 are transferred to the gates of the MOS transistors 3 through the transferring MOS transistors 4. At this time, on the pixel output lines 7, there appears the electric potential corresponding to the outputs formed by adding the signals to the reset outputs of the pixels (t6). In this state, when a High pulse is applied to the terminal 38, the outputs formed by adding the signals to the reset outputs of the pixels are stored in the capacitors 24 through the MOS transistors 26 (t7). The reset outputs of the pixels show variation because the threshold voltage values of the MOS transistors 3 of respective pixels have variation. Consequently, the differences between the outputs stored in the capacitors 23 and 24 are pure signals without noises. When the horizontal scanning circuit 34 is then operated, the output lines 35-1 and 35-2 turn to the High level in order, and the outputs stored in the capacitors 23 and 24 of respective columns are led to the horizontal output lines 27 and 28 through the MOS transistors 29 and 30, respectively. Before the outputs of the High level pulses onto the output lines 35-1 and 35-2, it is necessary to set the level of the terminal 36 to the High level to reset the horizontal output lines 27 and 28 through the MOS transistors 32 and 31, respectively, in advance. The pixel reset outputs and the signal outputs added to the pixel reset levels are input into the differential amplifier 39 through the horizontal output lines 27 and 28, and the reset levels are subtracted by the differential amplifier 39. Thus, pixel signal free of noises are output from the output terminal 40 (t8, t9).
Next, when the level of the output line 18-1 is turned to the Low level and the level of the output line 18-2 is turned to the High level by the operation of the vertical scanning circuit 17, the second row of the pixels is selected. The pulse timing for driving the second row of the pixels is the same as the timing for driving the first one.
In the operation described above, the potential of the reset potential supplying terminal 43 is determined according to the characteristics of the MOS transistors 3. An electric potential change is set so that only the source followers of the selected row operate and the MOS transistors 3 of the unselected row take their non-conductive states.
As described above, even if there are no selecting MOS transistors in pixels, the CMOS sensor can be operated, and thereby can output signals having high S/N ratios.
However, even the CMOS sensor described above as a conventional technique includes three MOS transistors in one pixel in addition to a photodiode. On the other hand, an interline type CCD, which is the most frequently used solid-state image pickup device, includes only a transferring gate and a vertical CCD in addition to a photodiode in one pixel. Consequently, the CMOS sensor is yet disadvantageous in comparison with the CCD for forming a small size pixel.
Moreover, Japanese Patent Publication Gazette No. H08-004131 discloses the sensor in which the base electrodes of bipolar transistors for amplifying pixel signals are connected in series in the row directions by MOS type transistors and the bases are reset by means of the MOS transistors.
Even this sensor requires the wiring for the control electrodes of resetting MOS transistors connected in the row directions, and consequently it is difficult to reduce the area of the pixels thereof.